发明名称 Pedestal level control circuit and method for controlling pedestal level
摘要 In order to reduce a circuit scale such as a brightness adjustment circuit or the number of pins in an IC chip, in the brightness adjustment circuit, a brightness adjusted video signal (internal video signal) output from an analog signal synthesis circuit or a D/A converter is input to one input terminal of a switch and a sample/hold circuit. The sample/hold circuit holds a voltage of a level in accordance with the pedestal level of the internal video signal at a timing in accordance with a sampling pulse in synchronization with the internal video signal. A clamp circuit clamps the pedestal level of an external video signal in accordance with a clamp pulse, using the voltage held by the sample/hold circuit as the reference voltage, and input it to the other input terminal. The output terminal of the switch is connected to an amplifier.
申请公布号 US2003001976(A1) 申请公布日期 2003.01.02
申请号 US20020184952 申请日期 2002.07.01
申请人 MATSUSHITA ELECTRIC INDUSTIAL CO., LTD. 发明人 SASADA MASAHIKO
分类号 H04N5/16;H04N5/44;H04N5/57;H04N9/72;H04N9/73;(IPC1-7):H04N5/16 主分类号 H04N5/16
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