Method for converting a logic circuit model

摘要

The states of a logic circuit block are set as operation start states and operation end states. An instruction to be analyzed is selected from input/output instruction information. An input signal corresponding to the selected instruction is applied to an RT (Register Transfer)-level model that is in the operation start state. Then, the input signal value applied to the RT-level model is changed. In order to extract operation of the logic circuit block, the RT-level model is analyzed until it reaches the operation end state. An operation model of the logic circuit block is produced based on the extracted operations. In this way, the model of the logic circuit block specifically described at RT level can be converted into a high abstraction-level model including no concept of time.