| 摘要 |
An apparatus (and method) is provided that pumps (up or down) the voltage on a memory cell thereby increasing (above the logic one voltage value) or decreasing (below the logic zero voltage value) the voltage stored in the memory cell, and providing an increased differential on the bit lines during a subsequent read operation of the memory cell. When a logic one or zero voltage is coupled to the first plate of the memory cell for storage, the second plate is held at a voltage that is lower or higher, respectively (preferably a voltage that is the complement logic value of the value being stored). After the word line is deactivated (thereby decoupling the memory cell from the bit line and storing a logic one voltage value or logic zero voltage value), the voltage on the second plate is correspondently either raised or lowered. In the present invention, the second plate is raised or lowered to the precharge and equilibrate value (usually Vdd/2). This pumps the voltage stored in the memory cell to a higher voltage (if a logic one is stored) or a lower voltage (if a logic zero is stored).
|
