发明名称 Semiconductor chip configuration and fabrication method
摘要 In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.
申请公布号 US2003003744(A1) 申请公布日期 2003.01.02
申请号 US20020187766 申请日期 2002.07.02
申请人 FRANKOWSKY GERD 发明人 FRANKOWSKY GERD
分类号 H01L21/302;H01L21/60;H01L23/31;H01L23/50;H01L23/522;H01L23/525;H01L29/00;(IPC1-7):H01L21/302 主分类号 H01L21/302
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