发明名称 Pipeline processor for complex vector operation
摘要 <p>In a complex vector operation processor for carrying out a complex vector operation, first and second multipliers (64-1, 64-2) are provided in parallel. The first multiplier calculates first product data of first data and second data, and the second multiplier calculates second product data of third data and fourth data. A first adder (66) is operatively connected with the outputs of the first and second multipliers to calculate first addition resultant data or first subtraction resultant data from the first and second product data. The second and third adders (70-1, 70-2) are operatively connected with the output of the first adder section and arranged in parallel. The second adder calculates second addition resultant data or second subtraction resultant data from fifth data and sixth data. The third adder calculates third addition resultant data or third subtraction resultant data from seventh data and eighth data. The data output section is operatively connected with the second and third adders to produce complex operation resultant data from two of the second addition resultant data, the second subtraction resultant data, the third addition resultant data, and the third subtraction resultant data. &lt;IMAGE&gt; &lt;IMAGE&gt;</p>
申请公布号 EP1271338(A2) 申请公布日期 2003.01.02
申请号 EP20020014250 申请日期 2002.06.26
申请人 NEC CORPORATION 发明人 KATAYANAGI, SATOSHI
分类号 G06F7/00;G06F9/302;G06F9/38;G06F17/14;G06F17/16;(IPC1-7):G06F17/14 主分类号 G06F7/00
代理机构 代理人
主权项
地址