Fast frame synchronization

摘要

A receiver for receiving synchronized digital transmissions organized in frames, each frame having a frame start, has a clock for generating pulses at time intervals with respect to a time reference and a counter for generating a count of the time intervals with respect to the time reference. A/D converters sample the digital transmission using the pulses from the clock. A cyclic prefix correlator detects the frame start during a count corresponding to an A/D sample. This count is indicative of the time interval during which the frame start was detected with respect to the reference. A memory is provided for storing a plurality (typically 36) counts indicative of the time interval during which the frame start was detected. A pointer is generated from the counts stored in memory. The pointer is indicative of a projected time interval during which a future frame start is expected to arrive. This projected time interval is computed by using a lead/lag digital filter and an oscillator responsive to the digital filter. One or more portions of the receiver are implemented using a programmable signal processor.