Semiconductor memory integrated circuit

摘要

An address buffer includes a latch circuit, and is controlled by an internal clock signal sent from a clock buffer. A decoding circuit section for selecting a word line is formed of a predecoder and a row decoder for further decoding a decoded output from the predecoder. The predecoder has no latching function, and the row decoder has a latch circuit. A pulse generating circuit generates two timing pulses based on a clock signal CK1. The activation of the row decoder is controlled by the two timing pulses.