发明名称 CBR/VBR traffic scheduler
摘要 A CBR/VBR traffic scheduler includes multiple CBR/VBR shapers to shape traffic over a wide range of peak cell rates for multiple CBR and VBR connection. Each shaper points to one or more VCs in a link list and includes a PCR counter initialized to a first value, an SCR counter initialized to a second and an arbitration counter. Each shaper is also connected to one of several clock sources, each having an associated clock cycle. A priority encoder, coupled to each arbitration counter, provides for determining priority between shapers having one or more associated VCs ready for transmission. Both the PCR counter and the SCR counter for each shaper is decremented during each associated clock cycle. For each shaper, when the PCR counter is decremented to a value of zero, the arbitration counter is initialized to a preset value and enabled for selection by the priority encoder. For each shaper, when the SCR counter is decremented to zero, a credit count parameter associated with each of the VCs in the associated link list is incremented by a predetermined value. The shaper having the lowest arbitration count value is selected by the priority encoder for cell transmission. When a shaper is selected for cell transmission, the associated link list of VCs is walked through in order. Only VCs that have a credit count parameter above a threshold value are transmitted.
申请公布号 US6501731(B1) 申请公布日期 2002.12.31
申请号 US19990344820 申请日期 1999.06.25
申请人 INTEL CORPORATION 发明人 CHONG SIMON;BLESZYNSKI RYSZARD;STELLIGA DAVID A.;HUANG ANGUO TONY
分类号 G06F9/46;H04L12/56;(IPC1-7):H04L12/56 主分类号 G06F9/46
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