SRAM HAVING TRIPLE POWER LINE

摘要

PURPOSE: An SRAM(Static Random Access Memory) having a triple power line is provided to reduce power consumption of a cell interface portion by using gate oxide layers having different thickness. CONSTITUTION: A memory array portion(30) includes a plurality of unit memory cells(30a) and receives the first a supply voltage through the first internal power line. A transistor of the unit memory cell(30a) has a gate oxide layer of the first thickness. A cell interface portion(20) includes driving circuits for driving the unit memory cells(30a) of the memory array portion(30) and receives the second supply voltage through the second internal power line. A transistor of the driving circuit has the gate oxide layer of the first thickness. A peripheral circuit portion(10) includes peripheral circuits driving an SRAM. A transistor of the peripheral circuit portion(10) has the gate oxide layer of the second thickness thicker than the first thickness. The first internal power circuit provides the first internal supply voltage. The second internal power circuit(51) includes a driving portion for driving the second internal supply voltage. Each setup voltage level of the first and the second internal supply voltages are lower than an external supply voltage level.