| 摘要 |
PURPOSE: To provide a semiconductor memory in which increment of circuit area is suppressed, and operation of which CAS latency is 1 and operation of which CAS latency is 2 or more are compatible. CONSTITUTION: A repeater circuit 30 outputs either first or second clock signals in accordance with whether CAS latency is 1 or 2 or more based on a clock signal transmitted from an internal clock generating circuit 16 by a clock signal line. The first clock signal has two times activation pulse in a cycle of an external clock. An input output circuit 200.2 responds to activation of the second clock signal in a state in which CAS latency is 2 or more, responds to activation of the first clock signal and an equalizing signal in a state in which CAS latency is 1, and stores read data.
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