| 摘要 |
The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.
|
