发明名称 Deferred correction of a single bit storage error in a cache tag array
摘要 Methods and apparatus defer correction of an error in a tag entry of a cache tag array. An address of requested data, including an address tag field, can be received by a cache. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated and result in outputting of a first data entry of a data array. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.
申请公布号 US6502218(B1) 申请公布日期 2002.12.31
申请号 US19990461243 申请日期 1999.12.16
申请人 INTEL CORPORATION 发明人 GEORGE VARGHESE;MROCZEK MICHAEL ROBERT
分类号 G06F11/10;G11C29/00;(IPC1-7):G11C29/00 主分类号 G06F11/10
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