Method of clock buffer partitioning to minimize clock skew for an integrated circuit design

摘要

A method of clock buffer partitioning includes the steps of receiving as input a description of a number of clock buffers for buffering a system clock to a plurality of clocked circuit elements; constructing a balanced clock tree from the description wherein the balanced clock tree includes a plurality of buffers in a hierarchy of buffer levels; partitioning each of the hierarchy of buffer levels into a plurality of buffer groups wherein clock skew in each of the plurality of buffer groups at each buffer level is substantially minimized; routing a clock input to a plurality of buffers within at least one of the plurality of buffer groups in at least one of the hierarchy of buffer levels to construct a zero clock skew among the plurality of buffers; calculating an estimated group insertion delay for the at least one of the plurality of buffer groups as a sum of an internal insertion delay and a downstream insertion delay of one of the plurality of clocked circuit elements; and generating as output the estimated group insertion delay.