MULTILEVEL CACHE SYSTEM

摘要

PURPOSE: A multilevel cache system is provided to control a second cache memory simply even if increasing a set number of a set-associated cache memory in order to compensate the reduction of the hit ratio due to the size reduction. CONSTITUTION: The system includes the first cache memory for storing a tag address and the data and the second cache memory(40) of the lower access priority by a processor than the first cache memory. The second cache memory includes a tag memory dividing into a plurality of sets(140-143) and storing the tags, and a data memory dividing into a plurality of sets(130-133) matching to the respective tag memory sets(140-143) and storing the data. Each set(140-143) of the tag memory includes the region storing the tag, the region storing the first information indicating the validity of the data stored in a matched data memory and the region storing the second information indicating that the data stored in the matched data memory is stored in the first cache memory. A control logic(160) performs the overall control for the second cache memory(40) and performs the control according to the mismatch based on the first and the second information when the access of the second cache memory(40) by the processor is mismatched.