| 摘要 |
Vertical transistor comprises a source region (103), a drain region (109), a gate region (108), and a channel region (104) arranged between the source region and the drain region. The source region, the channel region and the drain region are arranged in the vertical direction in a semiconductor substrate. The gate region has an electrical insulation to the source region, drain region and channel region. The gate region is arranged around the channel region in such a way that the gate and channel regions form a coaxial structure. An Independent claim is also included for a storage arrangement having several vertical transistors arranged next to each other in a storage matrix in a semiconductor substrate. Preferred Features: The electrical insulation between the channel region and the gate region is made from a succession of electrically insulating layers, preferably made from a first oxide layer, a nitride layer and a second oxide layer.
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