| 摘要 |
<p>A reconfigurable chip (20) is taught having reconfigurable functional units including a shift register, arithmetic logic, and multiplexers. The data paths are interconnected to other data path units. Interconnection is provided by transferring word length data. The shifter allows for the word length data to be adjusted for use in the arithmetic logic unit. Reconfigurable functional units are controlled by reconfigurable functional unit instructions. The reconfigurable unit instructions are stored in a reconfigurable functional unit instruction memory, which is addressed by a state machine on the chip.</p> |
