| 摘要 |
The buffer circuit (10) comprises two transistors, an n-MOS transistor (MN1) and a p-MOS transistor (MP1), connected in series between two supply-voltage terminals at determined potentials (Vdd, Gnd), where the latter potential is lower than the former. The sources of the two transistors are connected together and form the output (Z) of the buffer circuit, the gates are connected together and form the input (A) of the buffer circuit, the drain of the n-MOS transistor (MN1) is connected to the higher potential terminal (Vdd), and the drain of the p-MOS transistor (MP1) is connected to the lowre potential terminal (Gnd). The higher potential (Vdd) is a positive supply potential, and the lower potential (Gnd) is a negative supply potential or the potential of the ground. The difference between the two potentials (Vdd, Gnd) is slightly higher than the sum of the conducting voltage of the n-MOS transistor (MN1) and the conducting voltage of the p-MOS transistor (MP1). A memory cell comprises the buffer circuit (10) whose output is connected to the input so to form a latch. The memory cell in the first embodiment comprises a write-access transistor connected between the bit line and the input (A) of the buffer circuit, and a read-access transistor connected between the bit line and the word line and whose gate is connected to the output (Z) of the buffer circuit. The memory cell in the second embodiment comprises a write-and-read-access transistor connected between the bit line and the input (A) of the buffer circuit, and a read-protection transistor connected between the input (A) and the output (Z) of the buffer circuit.
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