Implementing semaphores in a content addressable memory

摘要

A network processor application-specific integrated circuit (ASIC) includes a plurality of processor devices each adapted to generate a semaphore operation request. A request arbiter, having connections to the plurality of processor devices, is provided to determine the semaphore operation request from one of the plurality of processor devices to be forwarded. A content addressable memory (CAM) is provided to store a data set. A CAM control state machine interconnects the request arbiter and the CAM, and implements a semaphore operation requested by one of the plurality of processor devices to the content addressable memory to access the data set.