发明名称 OUTPUT CIRCUIT WITH HIGH WITHSTAND VOLTAGE
摘要 PROBLEM TO BE SOLVED: To provide a output circuit with high withstand voltage capable of decreasing power consumption and preventing malfunction of a load. SOLUTION: This output circuit with high withstand voltage consists of an output stage circuit, i.e., a CMOS circuit 1 consisting of P1 on the HIGH side and N1 on the LOW side, and a preceding stage, i.e., a CMOS circuit 2 consisting of P2 and N2. An output signal Vout is outputted from an intermediate point of the circuit 1, and a load is driven by the signal Vout. The relation between thresholds of the P1 and P2 is set to Vtp1>Vtp2. By setting Vtp1>Vtp2, since P2 is turned on earlier than P1, P1 can be prevented from being turned on in the starting process of power supply voltage. Thus, malfunctions (malfunction of a load) of a plasma display can be prevented during its maintenance period, and power consumption of the output stage circuit can be reduced also.
申请公布号 JP2002374158(A) 申请公布日期 2002.12.26
申请号 JP20010179452 申请日期 2001.06.14
申请人 FUJI ELECTRIC CO LTD 发明人 SUMIDA HITOSHI
分类号 H03K19/0175;(IPC1-7):H03K19/017 主分类号 H03K19/0175
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