| 摘要 |
An 8F2 (2x2F wordline pitch by 2F bitline pitch) memory cell uses a vertical gate transistor having one gate driving two sources and two drains, one source and drain being formed on each side of the trench. Because two channels are provided, the device allows for sufficient current capacity, even with a 2F gate length. The memory cell array is formed in a series of active regions, corresponding to the bit lines of the array, which active regions are bounded by isolation trenches between the bit lines. The deep trenches segment the active regions and the overlying bit lines tie the cells of a given row together. Each memory cell has two drain regions, each having two contacts to the bit line and adjacent cells share one drain region, resulting in four contacts to the bit line for each memory cell. Support circuitry, including sense amplifiers
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