发明名称 |
PACKET PROCESSOR AND PACKET PROCESSING METHOD |
摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a memory capacity for packet accumulation to be provided within a packet selection device. SOLUTION: The processor is provided with the packet selection device 101 for determining whether a packet needs modifying, a write buffer 103 for accumulating the packet and a packet modifying device 111 for modifying the packet. The buffer 103 receives the packet from the device 101 to accumulate it and resends a packet write address to the device 101. The device 101 receives a packet write address from the buffer 103 and sends the packet and the packet write address to the device 111. The device 111 modifies the packet and writes the modified packet in the write buffer 103, in accordance with to the packet write address.</p> |
申请公布号 |
JP2002374310(A) |
申请公布日期 |
2002.12.26 |
申请号 |
JP20010181868 |
申请日期 |
2001.06.15 |
申请人 |
TOSHIBA CORP |
发明人 |
ISHII TSUTOMU;TOMIZAWA KENJI |
分类号 |
G11B20/10;H04L12/70;H04L13/08;(IPC1-7):H04L13/08;H04L12/56 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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