| 摘要 |
The invention relates to a vertical transistor (1) such as is used in a DRAM memory cell. In DRAM memory cells the individual memory cells are insulated from one another by an insulation trench (6) (STI). Since its channel region is insulated from a substrate (2) by the insulation trench (6), the vertical transistor (1) is configured as an SOI transistor by said insulation trench (6). The invention also relates to a system and to a method for connecting the channel region (5) of the vertical transistor (1) to the substrate (2) by providing a conductive layer (10) in the insulating trench (6) between a lower insulation filling (8) and an upper insulating filling (9). |
