| 摘要 |
A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacity formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacity which is formed on a third interlayer insulation film covering the bit line; a capacity contact which is formed through the third and second interlayer insulation film and makes a connection between the capacity and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.
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