| 摘要 |
A high-resolution, low-power wide-dynamic-range CMOS imager includes an array of pixel imaging cells, each of which embeds with a pixel transducing circuit at the pixel level a digital arithmetic logic processing circuit and a memory circuit. This permits multi-bit analog-to-digital conversion of an electromagnetic sensor output at the pixel level. The processing and memory circuits are usable on a pixel-parallel basis in conjunction with any type of pixel transducing circuit design that produces a binary output. The pixel processing and memory circuits may be configured with pixel transducing circuits in 2-dimensional arrangements on a single substrate or in 3-dimensional arrangements of three layered substrates, and may be used in multiplexed or non-multiplexed fashion with one or several pixel transducing circuits.
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