发明名称 |
Semiconductor integrated circuit device provided with a self-testing circuit for carrying out an analysis for repair by using a redundant memory cell |
摘要 |
A memory cell array is divided into a first and second sub-memory cell arrays. A built-in self-testing circuit is provided with an address replacement determining circuit which is installed in each of the first and second sub-memory cell arrays, and which, assuming that a selection of a memory cell from the first and second sub-memory cell arrays and a replacement thereof to a preliminary memory cell can be carried out mutually in an independent manner, makes a determination as to which preliminary memory cell is used for replacement, and outputs the result of determination.
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申请公布号 |
US2002196683(A1) |
申请公布日期 |
2002.12.26 |
申请号 |
US20020152689 |
申请日期 |
2002.05.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
OHTANI JUN;KAWAGOE TOMOYA |
分类号 |
G01R31/28;G11C11/401;G11C29/00;G11C29/04;G11C29/12;G11C29/44;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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