| 摘要 |
Disclosed is a peak hold circuit wherein output current corresponding to the peak value of input current is obtained for input currents with little change in magnitude, at essentially higher speeds. Detected drain current and input current of a P-MOS FET are compared, a first reference potential is applied to an NPN transistor, and a second reference potential lower than the first reference potential by a predetermined voltage such that the NPN transistor and a PNP transistor are not simultaneously turned on, is applied to the PNP transistor. In the event that the detected current is greater than the drain current, the NPN transistor is turned on and the PNP transistor is turned off, in the event that the detected current is smaller than the drain current, the NPN transistor is turned off and the PNP transistor is turned on, and in the event that the detected current and the drain current are equal, the NPN transistor and the PNP transistor are both turned off.
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