| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache memory controller capable of restoring a cache memory to a pre-reset state in an extremely short time even when the cache memory is reset during data supply processing when a cache mistake is generated. SOLUTION: When a cache mistake is generated in a line 118 to be read at the time of reading data from a cache memory 100, a valid bit 103 and a TAG part 102 of the line 118 in which the mistake is generated are made invalid under the control of a control part 21, and data having the same address as that of the read request are read from an external memory 200 to the line 118, and the valid bit 103 of the line 118 is made valid, and the address of the TAG part 102 is updated.
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