| 摘要 |
PROBLEM TO BE SOLVED: To provide a power MOS transistor which can have a desired sub strate potential, while being reduced in element area. SOLUTION: A channel region is formed in the surface layer of an N-type silicon substrate 1, and a source area is formed in the surface layer of the channel region. On the surface side of the N-type silicon substrate 1, a gate electrode is arranged at least to a portion of the channel region across a gate insulating film. On the top surface side of the N-type silicon substrate 1, a source electrode is arranged in contact with the source region through a contact hole. In neither the contact hole for a source nor a source cell at its peripheral part, a body contact region to be at the substrate potential is provided, a body contact region 14 is provided outside the source cell, and another electrode 15 is extended from the source electrode.
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