发明名称 QUANTIZATION METHOD FOR DIGITAL PHASE-LOCKED LOOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a quantization method for a digital phase-locked loop circuit that provides a quantized signal having small errors, even without the need for a high-speed clock signal. SOLUTION: Phase difference signals Vp1 , Vp2 , outputted from a phase comparator circuit 1, are fed to 1st and 2nd quantization circuits 2, 3, the 1st and 2nd quantization circuits 2, 3 quantize the phase difference signals Vp1 , Vp2 by using quantization clocks Φ1, Φ2, whose phases are deviated by 180 deg. by a delay circuit 7 and an adder 4 sums signals outputted from the 1st and 2nd quantization circuits 2, 3.
申请公布号 JP2002368606(A) 申请公布日期 2002.12.20
申请号 JP20010169306 申请日期 2001.06.05
申请人 NEC MIYAGI LTD 发明人 TANNO FUMIHIRO
分类号 H03L7/06;H03L7/091;H04L7/033 主分类号 H03L7/06
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