| 摘要 |
PROBLEM TO BE SOLVED: To solve the problems that a manual workload is large and a data amount increases in the circuit connection verification of the entire memory chip. SOLUTION: The layout data of the chip of a semiconductor memory cell are divided into a peripheral circuit and a memory cell matrix. Also, regarding the memory cell matrix among the divided peripheral circuit and memory cell matrix, the entire connection verification is performed for a decoder, the connection verification is performed within a constituting element for a common signal line and an intrinsic signal line in the constituting elements other than the decoder, and a unit circuit is taken out and the connection verification is performed. Further, the node names of the common signal line and the intrinsic signal line are transmitted between the adjacent constituting elements of the memory cell matrix. |
