发明名称 SIGNAL PROCESSOR AND DRIVING CONTROL METHOD FOR THE SAME
摘要 PROBLEM TO BE SOLVED: To immediately restore the inter-timing clock phase of a camera head side and a camera main body side to a positive phase when the phase is turned to be negative, and to automatically correct a power supply voltage to be supplied from the camera main body side to the camera head side in a head separation type 3CCD camera. SOLUTION: Timing clocks CKa and CKb to be outputted from timing generators 113 and 121 at camera main body 110 side and a camera ahead 120 side are phase-compared, and a clock generator 111 is controlled according to the phase compared output. The timing clock CKb to be outputted from the head side timing generator 121 is superimposed on DC components corresponding to a head side power supply voltage, and the DC components are extracted from the signal by the main body 110 side, and fed back to a voltage control type voltage booster 119 so that a stable power supply voltage can be obtained as the boosted power supply voltage, and transmitted form the main body 110 side to the head 120 side under the consideration of the influence of voltage drop due to a plurality of cable lengths.
申请公布号 JP2002369072(A) 申请公布日期 2002.12.20
申请号 JP20010176351 申请日期 2001.06.11
申请人 SONY CORP 发明人 ICHIHARA KENJI
分类号 H04N5/232;H04N5/225;H04N5/335;H04N5/341;H04N5/372;H04N7/18;H04N9/09;(IPC1-7):H04N5/232 主分类号 H04N5/232
代理机构 代理人
主权项
地址