发明名称 SEMICONDUCTOR AND MANUFACTURING METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor, having high throughput property and its manufacturing method which inserts a minimum required dummy pattern for improving high planarity, after CMP process. SOLUTION: In the semiconductor device has a surface planarized through chemical mechanical polishing, the semiconductor device surface is divided virtually into a plurality of regions to form a dummy pattern, having at least a difference of 10% or less between area proportions occupied by projecting or recessed regions of the divided regions; and a maximum to minimum ratio of 1.3 or less of proportions occupied by the projective or recessed regions of the divided regions or a difference of 30 nm or less, between a maximum height and a minimum height of the divided regions.
申请公布号 JP2002368103(A) 申请公布日期 2002.12.20
申请号 JP20010169544 申请日期 2001.06.05
申请人 HITACHI LTD 发明人 OTAKE ATSUSHI;KOBAYASHI KINYA
分类号 H01L23/52;H01L21/304;H01L21/3105;H01L21/3205;H01L21/768;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/822;H01L21/320 主分类号 H01L23/52
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