发明名称 LAMINATED CHIP INDUCTOR
摘要 PROBLEM TO BE SOLVED: To improve mounting stability and adhesion, and facilitate the verification of soldering upon mounting by conveniently forming external electrodes without using a dip process. SOLUTION: Electrically insulating layers and conductor patterns are alternately laminated, and the conductor patterns are sequentially connected to form a coil 20 superposed in the laminating direction within an electric insulator. The both ends of the coil are led out from the outer surface of the laminated chip 24 via lead out conductors 22. This device has terminal electrode patterns 26 so formed that they are in the same layers as the lead out conductors, and their edges are exposed at the end surface of the laminated chip and they are connected with the lead out conductors; and floating electrode patterns 28 so formed that they are in the different layers from the terminal electrode patterns, and their edges are exposed at the end surface of the laminated chip and they are not connected with the coil. The terminal electrode pattern and one or more layers of the floating electrodes are arranged on both ends of the laminated chip and their exposed parts constitute the external electrodes 30.
申请公布号 JP2002367833(A) 申请公布日期 2002.12.20
申请号 JP20010178045 申请日期 2001.06.13
申请人 FDK CORP 发明人 SUZUKI YASUO;OBA YOSHINARI
分类号 H01F17/00;H01F27/29;(IPC1-7):H01F27/29 主分类号 H01F17/00
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