发明名称 METHOD AND SYSTEM FOR A FULL-ADDER POST PROCESSOR FOR MODULO ARITHMETIC
摘要 A cipher processor consists of an exponentiator and a modulo processor. The modulo processor comprises an adder, operable to perform modular reduction, A mod N, or addition, A+B. The modulo processor may be used independently of the exponentiator. It may be used as a carry resolving adder for adding intermediate results in carry-save format. A mod N is calculated in an iterative way, where A is an 2n-bit operand, whereas N is a n-bit operand.
申请公布号 WO02101506(A2) 申请公布日期 2002.12.19
申请号 WO2002US18302 申请日期 2002.06.07
申请人 CORRENT CORPORATION;LANGSTON, VAUGHN, R.;TAKAHASHI, RICHARD, J.;LAHTI, GREGG, D. 发明人 LANGSTON, VAUGHN, R.;TAKAHASHI, RICHARD, J.;LAHTI, GREGG, D.
分类号 G06F7/72 主分类号 G06F7/72
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