发明名称 |
POWER FAULT ANALYSIS IN A COMPUTER SYSTEM |
摘要 |
<p>A power fault diagnostic mechanism is disclosed for a computer system having a power system that includes a controller. A variable is recorded in a non-volatile memory associated with the power system. The variable assumes a first state when the computer system is powered on and operating. The variable remains in the first state until it enters a second state when the computer system is powered off in response to a power-off request. The controller operates in a standby mode when the computer system is powered off. Upon being powered up, e.g., after a utility power disturbance, the controller reads the variable in the non-volatile memory. This allows determination of whether a disturbance has occurred, even when the computer system was powered off.</p> |
申请公布号 |
WO02101554(A2) |
申请公布日期 |
2002.12.19 |
申请号 |
WO2002GB02184 |
申请日期 |
2002.05.10 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED |
发明人 |
BERGLUND, NEIL, CLAIR;TIETJEN, JOHN, NICOLAUS |
分类号 |
G06F1/30;G06F1/28;G06F11/34;(IPC1-7):G06F11/28 |
主分类号 |
G06F1/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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