METHOD AND SYSTEM FOR PREDICTIVE MOSFET LAYOUT GENERATION WITH REDUCED DESIGN CYCLE

摘要

In one disclosed embodiment, a number of parameter values for an RF MOSFET are received. Examples of parameter values are style (212), bulk contact (216), finger width (204), finger length (206), number of fingers (208), current (210), and slice parameter values. From the received parameter values, a number of parasitic values for a subcircuit model of the RF MOSFET are determined. For example, parasitic resistor values and parasitic capacitor values of the RF MOSFET are determined. The parasitic resistor values and parasitic capacitor values are used in simulating the circuit comprising the RF MOSFET. An RF MOSFET layout is then generated that results in parasitic values that are the same as the parasitic values already used in simulating the circuit comprising the RF MOSFET. As such, the parasitic values of the RF MOSFET have already been taken into account in the initial circuit simulation.