发明名称 Methods and apparatus for computer bus error termination
摘要 In a computer system having a bus architecture, a system and process for isolating a device from a bus without interrupting system operation is described, the system including bus interface logic monitoring and reporting activity on the bus, isolation control logic receiving error signals from error detectors, and isolation switches through which devices are interconnected to the bus, the isolation switches allowing for the isolation of the devices from the bus. The isolation control logic determines the devices to be isolated responsive to the reported error and, in turn, transmits an isolation switch control signal to the isolation switch(es) associated with the identified device(s) to isolate those device(s) from the bus. In some embodiments, errors are reported by system software, input/output virtual address error detectors for systems using virtual memory addressing, protocol error detectors, and sensors sensing the physical removal of a bus-connected device from its bus interface slot.
申请公布号 US2002194548(A1) 申请公布日期 2002.12.19
申请号 US20010871180 申请日期 2001.05.31
申请人 TETREAULT MARK 发明人 TETREAULT MARK
分类号 G06F11/07;G06F11/30;H04L1/22;(IPC1-7):H04L1/22 主分类号 G06F11/07
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