发明名称 WAFER LEVEL CHIP SCALE PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 PURPOSE: A wafer level chip scale package and a method for manufacturing the same are provided to easily control the thickness of a metal wire and to simplify manufacturing processes without using a sputtering by forming a glue layer between a substrate and the metal wire. CONSTITUTION: A semiconductor chip(200) has a plurality of chip pads(202). A metal wire(209) is formed on the semiconductor chip(200) and has an opening(214) for exposing the chip pad(202) and a ball land(210). A glue layer(206) is formed between the semiconductor chip(200) and the metal wire(209). A conductive layer(216) is filled in the opening(214) so as to electrically connect with the chip pad(202) and the metal wire(209). A molding body(230) is covered to the metal wire and the conductive layer, and exposed the ball land(210). A conductive ball(220) is formed on the exposed ball land and mounted on a substrate(240).
申请公布号 KR20020094594(A) 申请公布日期 2002.12.18
申请号 KR20010032874 申请日期 2001.06.12
申请人 HYNIX SEMICONDUCTOR INC. 发明人 BAEK, HYEONG GIL
分类号 H01L23/52;H01L21/3205;H01L23/12;H01L23/28;H01L23/31;H01L23/485 主分类号 H01L23/52
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