发明名称 LINEARIZATION METHOD OF VARIABLE DELAY CIRCUIT, TIMING GENERATOR AND SEMICONDUCTOR TESTING DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a technology capable of determining the matching or non-matching between the phase of a shift clock and the phase of a delay clock, even when phase jitters in the linearizing operation of a variable delay circuit are included when the shift clock is used. SOLUTION: The phase of the shift clock is made to match with the offset phase of the delay clock to detect the offset, and path selection data in the offset detection are stored in a linearization memory. The phase of the shift clock is shifted in a normal direction by clock resolution portion, and the phase of the delay clock is shifted in reverse in the direction opposite to the normal direction once. The phase of the shift clock is then compared with the phase of the delay clock, the path selection data are changed to shift the phase of the delay clock in the normal direction, until both the phases match, and the path selection data in the matching of both the phases are stored in the linearization memory.
申请公布号 JP2002365345(A) 申请公布日期 2002.12.18
申请号 JP20010177419 申请日期 2001.06.12
申请人 ADVANTEST CORP 发明人 SATOU SHINYA
分类号 G01R31/3183;(IPC1-7):G01R31/318 主分类号 G01R31/3183
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