发明名称 SEMICONDUCTOR DEVICE, TESTING METHOD OF THE SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE TESTING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor device capable of shortening the time for testing, to two or more memory circuits with few misjudgment. SOLUTION: An address decoder 12 generates two or more selection signals SEL0-SEL3, so as to simultaneously select first to fourth memory circuits RAM 0-RAM3, on the basis of an address signal ADD for accessing to the memory circuit by a CPU 11 in testing mode. A multiplexer 13 outputs the read data from the one memory circuit to be accessed by the CPU 11 to the CPU 11. The CPU 11 confirms whether write data match the read data, and outputs a confirmation signal K1. A comparator 14 compares the read data RD0-RD3 read from the memory circuits RAM0-RAM3, respectively, and outputs a judgment signal K2.
申请公布号 JP2002365338(A) 申请公布日期 2002.12.18
申请号 JP20010174101 申请日期 2001.06.08
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 TAKESHIGE MASAYUKI;HIBINO SUMITAKA;YAMADA KENJI
分类号 G01R31/28;G11C29/40;(IPC1-7):G01R31/28 主分类号 G01R31/28
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