发明名称 CHIP SCALE PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <p>PURPOSE: A CSP(Chip Scale Package) and a method for manufacturing the same are provided to enhance a bonding intensity of a metal wire and to simplify manufacturing processes. CONSTITUTION: Chip pads(202) are formed on a semiconductor chip(200). A first insulating layer(204) is formed on the semiconductor chip(200) and has an opening for exposing the chip pads. A metal wire(214) is electrically connected to the chip pad(202) by filling the opening. A second insulating layer(206) is formed on the first insulating layer(204) so as to expose the metal wire(214). A solder ball(218) is formed on the exposed metal wire(214) and mounted on a substrate(220). The second insulating layer(206) is an epoxy or a silicon rubber.</p>
申请公布号 KR20020094593(A) 申请公布日期 2002.12.18
申请号 KR20010032873 申请日期 2001.06.12
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, SIN
分类号 H01L23/12;H01L23/31;H01L23/48;H01L23/49;(IPC1-7):H01L23/48 主分类号 H01L23/12
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