| 摘要 |
In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. In such a package, the magnitude of the current flowing through the highest current power pin may be reduced by configuring the resistance of the power plane(s) and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in a package power plane to alter the current path and raise the impedance of the conduction path between some of the package power pins and the internal contact pads otherwise having the lowest impedance. If the package, such as a pin-grid-array package, includes more than one row of pins along an edge of the package, the internal package vias may be arranged to provide an impedance from die footprint to the outer row of pins which is not substantially higher than that of the inner row of pins. In this fashion the aggregate current carrying capacity of the carrier may be increased by reducing the difference in current flow between power pins having the highest current flow and power pins having the lowest current flow. The current flow through all the power pins may then be operated nearer to the design maximum of the particular connector used, or the design maximum of the carrier itself. |
