发明名称 |
Intermediate-grain reconfigurable processing device |
摘要 |
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.
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申请公布号 |
US6496918(B1) |
申请公布日期 |
2002.12.17 |
申请号 |
US20010892812 |
申请日期 |
2001.06.27 |
申请人 |
MASSACHUSETTS INSTITUTE OF TECHNOLOGY |
发明人 |
DEHON ANDRE;MIRSKY ETHAN;KNIGHT, JR. THOMAS F. |
分类号 |
G06F15/80;(IPC1-7):G06F9/00 |
主分类号 |
G06F15/80 |
代理机构 |
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地址 |
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