发明名称 |
Method of datapath cell placement for an integrated circuit |
摘要 |
A method of datapath cell placement is disclosed that minimizes signal propagation time through a datapath macro and datapath macro area that includes the steps of receiving a datapath description of constrained input pins, unconstrained input pins, and output pins for a datapath block; assigning a first corresponding first cell level to a first datapath cell in a data path of a constrained input pin wherein the first corresponding first cell level is representative of a number of intervening datapath cells between the first datapath cell and the constrained input pin; assigning a second corresponding first cell level to a second datapath cell in a data path connecting the first datapath cell to an unconstrained input pin that is substantially identical to the first corresponding first cell level; and assigning a corresponding second cell level to the datapath cell in the data path connecting the first datapath cell to the unconstrained input pin wherein the second cell level is representative of a number of intervening datapath cells between the datapath cell in the data path of the unconstrained input pin and the unconstrained input pin.
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申请公布号 |
US6496967(B1) |
申请公布日期 |
2002.12.17 |
申请号 |
US20010805642 |
申请日期 |
2001.03.13 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
TETELBAUM ALEXANDER;YU QIONG J. |
分类号 |
G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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