发明名称 Transaction checking for system architecture validation
摘要 A method and apparatus for a transaction checking for system architecture validation are provided. Tracking data is received from trackers in the system. The tracking data is parsed to construct queues. These queues are compared with each other. For one embodiment, the queues are further compared with predicted behavior of the element that was tested. Discrepancies between the queues and the queue and predicted behavior are flagged.
申请公布号 US6496792(B1) 申请公布日期 2002.12.17
申请号 US19980111126 申请日期 1998.07.06
申请人 INTEL CORPORATION 发明人 MAGNUSSON ERIC J.
分类号 G06F11/26;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F11/26
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