| 摘要 |
A PLL comprising a VCO, a phase comparator, a frequency comparator and a filter realizes an enlarged pull-in frequency range and increased operating frequency. The VCO generates a first clock signal and a second clock signal whose frequency is the same as that of the first clock signal and whose phase is ahead of that of the first clock signal. An input data signal is inputted to the phase comparator and the frequency comparator. The first clock signal is supplied to the phase comparator and the frequency comparator, and the second clock signal is supplied to the frequency comparator. The phase comparator executes phase comparison between the first clock signal and the input data signal, and outputs the result of the phase comparison. The frequency comparator which is composed of digital components executes frequency comparison between the clock signal and the input data signal based on the timing when the first clock signal changes its value and the value of the second clock signal at the timing, and outputs the result of the frequency comparison. The filter removes high frequency components from the outputs of the phase comparator and the frequency comparator and adds them together and thereby generates a control signal for controlling the oscillation frequency of the voltage controlled oscillator.
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