| 摘要 |
PURPOSE: To solve the problem, in a mirror-like logic, in which a control terminal 1 is connected to a gate electrode of an FET 2 and a control terminal 2 is connected to a gate electrode of a gate electrode 1, a resistor having to be connected in an X-shape, the resistor is arranged the periphery of a chip, and resulting in a large chip size. CONSTITUTION: Two parallel resistors are arranged between a common input terminal and an FET. Further, the resistor is formed of an n+ type impurity region, and some FETs are arranged between a control terminal and an output terminal, thereby realizing a mirror switch circuit, having the same chip size as that of a normal pattern.
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