APPARATUS FOR CIRCUIT VERIFICATION

摘要

PROBLEM TO BE SOLVED: To verify a circuit on a single-chip circuit level with efficiency and high accuracy and especially perform a logical verification on an RTL(register transfer level) with efficiency. SOLUTION: An apparatus 150 for circuit verification comprises a test vector supply means A 161 which supplies an input signal group A (signals for testing) 103 into a single-chip circuit 100, an expected value generating means A 151 and an expected value generating means B 152 corresponding respectively to more than one block (a block A 101 and a block B 102) constituting the single chip circuit and an expected value comparison means B 172. These expected value generating means are composed in the same connection mode as the blocks in the single chip circuit to generate expected values by using the input supply group A supplied from the test vector supply means A. The expected value comparison means B compares and verifies an output signal group B 105 from a block at the bottom layer with an expected value B 154 outputted from the expected value generating means corresponding to the block in the block B 102.