| 摘要 |
<p>PROBLEM TO BE SOLVED: To increase read-out speed by reducing a wiring load of a redundant storage circuit and to reduce layout area, that is, chip area by removing an unnecessary layout region. SOLUTION: In a redundant storage circuit 5, series circuits of a memory cell TGF comprising floating gate transistors in which replacement information (e.g. defective address or the like) is electrically writable or erasable and respective selection transistors T151-T153 are arranged for each bit line B of a main storage circuit 4, the device is constituted so that one side end of a memory cell TFG for storing replacement information and any of bit lines B of the main storage circuit 4 is electrically connected or freely cut off by any of the selection transistors T151-T153 and write-in and read-out current can be supplied to the memory cell TGF for storing replacement information through the bit lines B.</p> |
