| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a high integration nonvolatile semiconductor memory in which one memory cell has two trap sites. SOLUTION: The nonvolatile semiconductor memory comprises a plurality of memory cells 100, each having two MONOS memory cells being controlled by a word gate and control gate 106A and 106B, arranged in first direction and second direction B. Two control gate lines 106B and 106A being connected commonly with one sub-control gate line has a wide inter-line region 107A, a common connection region 107B of two lines, and a narrow inter-line region 107C arranged in a region other than the wide inter-line region and the common connection region. The wide inter-line region 107A is an enlarged line width region 111 of a bit line 110 and provided with a contact 107F, and the common connection region 107B is a discontinuous region 107E of the bit line 110.</p> |
